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2010 Microchip Technology Inc.

Preliminary

DS41350E-page 143

PIC18F/LF1XK50

15.2.3

ENABLING SPI I/O

To enable the serial port, SSP Enable bit, SSPEN of the

SSPCON1 register, must be set. To reset or reconfig-

ure SPI mode, clear the SSPEN bit, reinitialize the

SSPCON registers and then set the SSPEN bit. This

configures the SDI, SDO, SCK and SS pins as serial

port pins. For the pins to behave as the serial port func-

tion, some must have their data direction bits (in the

TRIS register) appropriately programmed as follows:

SDI is automatically controlled by the SPI module

SDO must have corresponding TRIS bit cleared

SCK (Master mode) must have corresponding

TRIS bit cleared

SCK (Slave mode) must have corresponding

TRIS bit set

SS must have corresponding TRIS bit set

Any serial port function that is not desired may be

overridden by programming the corresponding data

direction (TRIS) register to the opposite value.

15.2.4

TYPICAL CONNECTION

Figure 15-2 shows a typical connection between two

microcontrollers. The master controller (Processor 1)

initiates the data transfer by sending the SCK signal.

Data is shifted out of both shift registers on their pro-

grammed clock edge and latched on the opposite edge

of the clock. Both processors should be programmed to

the same Clock Polarity (CKP), then both controllers

would send and receive data at the same time.

Whether the data is meaningful (or dummy data)

depends on the application software. This leads to

three scenarios for data transmission:

Master sends data

–Slave sends dummy data

Master sends data

–Slave sends data

Master sends dummy data

–Slave sends data

FIGURE 15-2:

TYPICAL SPI MASTER/SLAVE CONNECTION

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

MSb

LSb

SDO

SDI

Processor 1

SCK

SPI Master SSPM<3:0> = 00xx

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

LSb

MSb

SDI

SDO

Processor 2

SCK

SPI Slave SSPM<3:0> = 010x

Serial Clock

Slave Select

General I/O

(optional)

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